| Selected publications |
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| 1 | Artykuł 2023
Piotr Patronik, Stanisław J Piestrak,| Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1}. EURASIP Journal on Advances in Signal Processing. 2023, vol. 2023, art. 92, s. 1-28. ISSN: 1687-6180 | | Zasoby:DOIURLSFX |     |
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| 2 | Artykuł 2021
Mikhail Babenko, Stanisław J Piestrak, Nikolay Chervyakov, Maxim Deryabin,| The study of monotonic core functions and their use to build RNS number comparators. Electronics. 2021, vol. 10, nr 9, art. 1041, s. 1-14. ISSN: 2079-9292 | | Zasoby:DOIURLSFX | |
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| 3 | Artykuł 2020
Mikhail Babenko, Maxim Deryabin, Stanisław J Piestrak, Piotr Patronik, Nikolay Chervyakov, Andrei Tchernykh, Arutyun Avetisyan,| RNS number comparator based on a modified diagonal function. Electronics. 2020, vol. 9, nr 11, art. 1784, s. 1-16. ISSN: 2079-9292 | | Zasoby:DOIURLSFX | |
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| 4 | Artykuł 2018
Piotr Patronik, Stanisław J Piestrak,| Design of RNS reverse converters with constant shifting to residue datapath channels. Journal of Signal Processing Systems for Signal Image and Video Technology. 2018, vol. 90, nr 3, s. 323-339. ISSN: 1939-8018 | | Zasoby:DOISFX | |
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| 5 | Referat konferencyjny 2017
Piotr Patronik, Stanisław J Piestrak,| Design of residue generators with CLA/compressor trees and multi-bit EAC. W: LASCAS 2017 : 8th Latin American Symposium on Circuits and Systems : Bariloche, Argentina, February 20-23, 2017 : R9 IEEE CASS Flagship Conference : proceedings / CAS - IEEE Circuits and Systems Society. [Danvers, MA] : IEEE, cop. 2017. s. 1-4. ISBN: 978-1-5090-5859-4 | | Zasoby:DOI |  |
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| 6 | Artykuł 2017
Piotr Patronik, Stanisław J Piestrak,| Hardware/software approach to designing low-power RNS-enhanced arithmetic units. IEEE Transactions on Circuits and Systems. 1, Regular Papers. 2017, vol. 64, nr 5, s. 1031-1039. ISSN: 1549-8328 | | Zasoby:DOISFX | |
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| 7 | Artykuł 2017
Piotr Patronik, Stanisław J Piestrak,| Design of reverse converters for a new flexible RNS five-moduli set {2k , 2n − 1,2n + 1,2n+1 − 1,2n−1 −1} (n Even). Circuits, Systems, and Signal Processing. 2017, vol. 36, nr 11, s. 4593–4614. ISSN: 0278-081X | | Zasoby:DOISFX | |
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| 8 | Referat konferencyjny 2016
Piotr Patronik, Stanisław J Piestrak,| Design of a low-power RNS-enhanced arithmetic unit. W: LASCAS 2016 : VII IEEE Latin American Symposium on Circuits and Systems : R9 IEEE Cass Flagship Conference, February 28 to March 2, 2016 / Pedro Julián, Andreas G. Andreou (eds.). Danvers, MA : IEEE, cop. 2016. s. 151-154. ISBN: 978-1-4673-7835-2 | | Zasoby:URL | |
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| 9 | Referat konferencyjny 2015
Sébastien Pillement, Stanisław J Piestrak,| Fault-aware configurable logic block for reliable reconfigurable FPGAs. W: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 24-27, 2015. [Danvers, MA] : IEEE, cop. 2015. s. 2732-2735. ISBN: 978-1-4799-8391-9 | | Zasoby:DOI | |
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| 10 | Artykuł 2015
Stanisław J Piestrak,| A note on RNS architectures for the implementation of the diagonal function. Information Processing Letters. 2015, vol. 115, nr 4, s. 453-457. ISSN: 0020-0190; 1872-6119 | | Zasoby:DOISFX | |
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